Search
Search Results
-
Transactions on High-Performance Embedded Architectures and Compilers V
Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods...
-
Building application-specific operating systems: a profile-guided approach
Although operating system optimization has been studied extensively, previous work mainly focuses on solving performance problems. In the cloud era,...
-
An Energy-Efficient Computing Approach by Filling the Connectome Gap
This paper presents an energy-efficient neuromorphic computing approach by filling the connectome gap between algorithm, brain, and VLSI. The gap...
-
Scalable-Grain Pipeline Parallelization Method for Multi-core Systems
How to parallelize the great amount of legacy sequential programs is the most difficult challenge faced by multi-core designers. The existing...
-
Transactions on High-Performance Embedded Architectures and Compilers III
Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for...
-
Transactions on High-Performance Embedded Architectures and Compilers IV
Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for...
-
Extracting More Parallelism: the 3D-Wave
If higher performance is required, a parallel application developer might have to extract more parallelism than initially employed in the...
-
Feedback-Based Global Instruction Scheduling for GPGPU Applications
In the face of the memory wall even in high bandwidth systems such as GPUs, an efficient handling of memory accesses and memory-related instructions...
-
Exploiting Parallelism: the 2D-Wave
In the previous chapter we have analyzed various parallelization approaches for H.264 decoding and concluded that in order to scale to a large number...
-
Eighth MEDEA Workshop
It is our pleasure to welcome you to this special section of Transactions on High-Performance Embedded Architectures and Compilers (HiPEAC),...
-
Cache Efficiency and Scalability on Multi-core Architectures
Two electrical engineering applications from industry partners dealing with sparse matrices were analyzed regarding cache efficiency and scalability...
-
Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores
Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level...
-
A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors
A systematic approach to customising Homogeneous Multi-Processor (HoMP) architectures is described. The approach involves a novel design space...
-
-
MorphoSys reconfigurable hardware for cryptography: the twofish case
This paper presents the mapping and performance analysis of the Twofish algorithm on MorphoSys. MorphoSys is a reconfigurable architecture that can...
-
OTAWA: An Open Toolbox for Adaptive WCET Analysis
The analysis of worst-case execution times has become mandatory in the design of hard real-time systems: it is absolutely necessary to know an upper...
-
Improved Scalability by Using Hardware-Aware Thread Affinities
The complexity of an efficient thread management steadily rises with the number of processor cores and heterogeneities in the design of system...
-
A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems
Future systems are not only heading towards increased parallelism, but also embrace heterogeneity and reconfigurability. We therefore present an...
-
A Hardware Task Scheduler for Embedded Video Processing
Modern embedded Systems-on-a-Chip deploy multiple programmable cores to meet increasing performance requirements of video, graphics, and modem...
-
Parallel H.264 Decoding on an Embedded Multicore Processor
In previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is...